Synchronization in (telecom) networks is the process of aligning the time scales of transmission and switching equipment, so equipment operations occur at the correct time and in the correct order. Synchronization requires the receiver clock to acquire and track the periodic timing information in a transmitted signal.
The transmitted signal consists of data that is clocked out at a rate determined by the transmitter clock. Signal transitions between zero and peak values contain the clocking information and detecting these transitions allows the clock to be recovered at the receiver. The recovered clock is used to write the received data into a buffer, also called elastic store or circular shift register, to reduce jitter. The data is then read out of the buffer onto a digital bus for further multiplexing or switching.
Synchronization at AimValley
Synchronization is a fundamental technology building block with AimValley for many years already. Practically every service provider network requires it, not because networks require the synchronization but mainly to provide, at the edge of the network, a frequency or phase/Time of Day synchronization singal to end-customers.
The performance of the traditional wired T1/E1, SONET and SDH networks are based upon constrained clock control theory and PLL design and deliver a frequency synchronization to the edge of the network. Also Circuit Emulated Services (CES) require frequency synchronization at the edge of the network to recover the emulated service via Differential Clock Recovery (DCR) methods.
Presented at Conferences
ITSF 2014, ITSF 2015, WSTS 2015
IEEE1588 BC versus TC
PRTC Architectural Options in a Telecom Network
AimValley Synchronization Expertise
AimValley provides a wide range of expertise regarding synchronization. From helping you to interpret and understand the various Standards to architectural support.
SONET/SDH/CES/CEP transmission technologies
* Timing architecture of various systems
* Core ASICs used in various systems
* SEC/Stratum-3 built into AimValley ASICs (Maximux, Matterhorn)
* IP blocks with Circuit Emulation Services (FPGA)
* Smart SFPs with CES (E1, DS1, 155Mb/s, 622Mb/s, 2488Mb/s
Architecture and implementation of products
* EEC-1/EEC-2 clocks
* IEEE1588 TC, BC, BMC
* Calculation of PLL bandwidth for synchronization function
Audio Video Bridging & Time Sensitive Networking