Technology – FPGA Packet Processing

Enabling flexible and high speed data off-load!

Packet processing is a critical function at all levels in the modern network infrastructure, supporting traffic classification, protocol implementation as well as security functions. Increasingly higher line rates demand advanced hardware assisted packet processing solutions, and the constantly evolving functions and protocols call for programmability of these solutions.

Field Programmable Gate Array (FPGA) devices provide a natural technology fit for the implementation of high-speed programmable packet processing, e.g. using an FPGA on a Network Interface Card (NIC), often called a Smart NIC card. Instead of using CPU cores for packet processing, such as filtering, flow lookup and protocol handling, these functions can be delegated to the FPGA. Also other CPU intensive tasks such as wire-rate encryption or content processing, compression and reduplication can all be done on the FPGA, freeing up valuable CPU cores for end-user application level processing.

Another benefit of FPGA based Smart NIC cards is the capability to support non-standard interfaces to enable video capture, legacy telecom or industry control inter-faces. Such solutions would eliminate the need for external and proprietary conversion equipment, and enable compact and cost effective system solutions with all the benefits of standard server platforms, software and management.

Unique capabilities with FPGA

FPGAs are typically used to resolve complex calculation tasks with unsurpassed performance due to massive parallel compute capability and high I/O bandwidth. The functionalities and attributes of FPGA can be combined on a single chip to enable uniquely differentiated packet processing solutions:

  • Heterogeneous compute with memory and DSP
  • Fixed latency, providing true real-time results
  • High I/O rates, and flexible protocol off-load
  • Streaming and signal processing algorithms
  • Machine Learning inference
  • Data-flow algorithms and arbitrary data width
  • In-field reconfiguration and upgrade

AimValley FPGA Packet Processing Expertise

A challenge has been the difficult programming model for FPGAs. Unlike CPUs and GPUs, FPGAs require expertise with dedicated programming languages such as VHDL or Verilog and design tools for synthesis and verification. These are covered by AimValley’s experienced design team that has delivered 100s of FPGA and ASIC designs, and created an extensive library of field-strength logic functions, accumulating millions lines of source code.

AimValley provides a wide range of expertise regarding FPGA-based Packet Processing:

  • Protocol conversion and tunneling, such as Ethernet to serial, video streaming via packet network, or IP over OTN; and support for multiple legacy protocol translations for Telecom or Industrial equipment.
  • Packet generation and monitoring, for multiple data flows, creating test patterns, e.g. for test and measurement equipment, or for on-line network quality monitoring and service assurance systems.
  • High bandwidth packet processing, supporting data rates at 100, 400 up to 800 Gb/s, utilizing a high performance packet processing pipeline and very wide on-chip data bus.
  • Productivity tools such as HLS and P4 to deliver complex designs with high flexibility and meeting the required quality in a shorter time-to-market
  • Consultancy and architectural support, for example selection of FPGA chip vendor and device family, high speed transceivers, and memory subsystem solutions, including on-chip High Bandwidth Memory (HBM).

AimValley proven track record

Our FPGA based packet processing designs are success-fully deployed in many products across telecom, industrial and transportation sectors. The solution often includes our hardware board design, software drivers, protocol stacks, or system level test. Examples of FPGA enabled product designs and technologies are:

Need Help?

WE'RE Here To Assist You

Feel free to contact us, and we will be more than happy to answer all of your questions and provide a demo.