Customer
A global provider of communication software, IP, and optical networking solutions engaged AimValley to provide Design Services to develop FPGAs and software on next-generation DS3 and OC48 line cards on their Packet Optical systems.
Customer Objectives
For this project, the customer identified and chose AimValley to leverage our expertise in DS3, SONET/SDH, and TDM over Packet to replace obsolete devices on their line cards. The expectation was to deliver FPGA designs offering 4x the number of ports and channels while maintaining feature parity with their current solutions.
AimValley Solution
AimValley delivered designs that included:
- Multiple OC3/OC12/OC48 ports and DS3 line interfaces, mappers, framers, converted via CEP/SAToP to packet streams into dual 10GE backplane.
- Software development to create the associated PCIe driver complete with the API.
- Line and Equipment Protection function, Fault and Performance Monitoring and Sync reference.
Key Technologies
- High-density TDM over Packet in FPGA
- DS3 line interfaces, framing and M13 multiplexer
- Multi-rate SONET/SDH framer
- Flexible TDM cross-connect
- High-speed interface to data buffer in DDR4 RAM
- Software driver with function-based API
- AMD High-End FPGA
Results and Added Value
Efficient
AimValley's previous experience and IP cores for TDM circuit emulation, DS3 and SONET/SDH, reduced the time to develop the solution, lowered costs, with confidence that this solution will perform well.
Successful
This program delivered the solutions in rapid succession with multiple releases to add addional features. We worked with the customer to select future-proof FPGAs that allow for additonal functionality in later phases of their project.
Partnership
AimValley engineers worked with customer's R&D team to define and deliver API integration in the customer's host software and to create and deliver the FPGA designs in close co-operation with the overall hardware/system design teams.
Innovation
Our solutions replaced multiple obsolete ASICs with a single AMD FPGA which reduced cost, size and power requirements. Several IP cores were rearchitected and optimized for the latest FPGA technology to support higher clock rates enabling quadrupled port and channel density.
