Project Example – ASIC to FPGA (EoL)


End of Life for merchant silicon chips or ASIC components is a constant struggle for many equipment manufacturers, especially when product longevity of 15 years or more is the norm, for example in the telecom, healthcare, and energy industries. A supplier announces a discontinued availability of a component and consequently, customers scramble for replacement parts or are forced to do a redesign of their product to ensure continued supply of systems.


Customer Objectives

A Tier 1 Telecom network operator had been deploying our multiplexer system as a standard business access solution for many years when End of Life was announced for a critical ASIC in our product. The customer quarterly demand planning remained constant for several more years, and the introduction of an alternate multiplexer product was considered too costly and would take years to integrate into an existing environment.

Customer Benefits

By using an FPGA to replace an End-of-Life ASIC component, the manufacturing and supply of the product could be guaranteed for several more years. The change required the introduction of a new order code for the affected board, but there was no need for new product certification, product verification testing, or any changes to the network management systems. Also, installation procedures or deployment practices remained as before the change.

AimValley Solution

We converted our EoL ASIC to an FPGA. All the submodules were immediately available as reusable assets. As an additional benefit, we could provide a short turnaround time for an FPGA design for a new customer who wanted a similar product.

Key Technologies

Design Briefs

Results and Added Value


The new FPGA-based board design could be released to manufacturing within 12 months after the End-of-Life was announced, preventing out of stock systems for the network operator.


The customer could quickly introduce the new solution, only requiring an update in their ordering system for the new board type.


FPGA and Hardware design teams worked closely together to ensure that the new board would be 100% software compatible and work in the existing system backplane without any restrictions.


The high-speed transceivers in the original ASIC were transfered to equivalent functionality in AMD Kintex technology. The signal levels, impedance and jitter performance were extensively simulated, verified and lab tested. The thermal design required extra attention, using a custom designed heatsink to ensure the extra power dissipation from the FPGA would be compatible with the passive cooling solution of the system.

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