Innovation at its Core

United States patent and trademark office

Patent number  : 9942025

Patent date         : April 10, 2018

Assignees            : OE Solutions Co. Ltd., AimValley B.V.

Inventor              : Willem van den Bosch, Niels Schipper

Electrical transceiver for synchronous Ethernet

Outline of the patent
Disclosed is an electrical transceiver for synchronous Ethernet, including: a first interface connected with a host; a second interface including a physical layer (PHY) transceiver connected with a serial link; and a processor connected with the first interface and the second interface, wherein the processor includes a timing control unit controlling a transmission signal, transmitted to the second interface from the first interface and a reception signal transmitted to the first interface from the second interface, to have the same time delay.

Method and apparatus for controlling delay in a device for transporting packets over optical transport network

Outline of the patent
A method and apparatus for controlling delay over a data path in a device for transporting Ethernet packets over an optical transport network. The device is configured to receive an incoming clock signal having a first frequency and an incoming data signal and to output an outgoing clock signal having a second frequency and an outgoing data signal. One or more delays over the data path in the device are measured in a predetermined measurement period. A phase adjustment amount is determined based on the one or more measured delays over the data path in the predetermined measurement period, and based on the determining phase adjustment amount, a phase of the outgoing clock signal is adjusted by a phase locked loop in such a way that the delay over the data path in the device is substantially equal to a fixed delay value.

United States patent and trademark office

Patent number  : 10447418B2

Patent date         : October 15, 2019

Assignees            : AimValley B.V.

Inventor              : Willem van den Bosch

United States patent and trademark office

Patent number  : 10523203

Patent date         : December 31, 2019

Assignees            : OE Solutions Co. Ltd, AimValley B.V.

Inventors            : Christiaan Hoede, Rob Farla

Adaptive power saving in field programmable gate array (FPGA) in optical module

Outline of the patent
An apparatus for saving power in an field programmable gate array (FPGA) in an optical communication device is provided. The apparatus includes at least one ring oscillator having an operating frequency disposed inside the FPGA, a core voltage switching unit configured to supply a core operating voltage to the FPGA and control logic configured to adaptively output an adjusted new core voltage to the FPGA via the core voltage switching unit. The control logic is configured to output a core voltage control signal to the core voltage switching unit based on the operating frequency of at least one ring oscillator. The core voltage switching unit is further configured to supply the adjusted new core voltage to the FPGA in accordance with the core voltage control signal.