Electrical transceiver for synchronous Ethernet
Outline of the patent
Disclosed is an electrical transceiver for synchronous Ethernet, including: a first interface connected with a host; a second interface including a physical layer (PHY) transceiver connected with a serial link; and a processor connected with the first interface and the second interface, wherein the processor includes a timing control unit controlling a transmission signal, transmitted to the second interface from the first interface and a reception signal transmitted to the first interface from the second interface, to have the same time delay.