High Level Features

  • TDM over Packet gateway for 16 DS1/E1 and fully channelized OC-3/STM-1
  • CESoPSN and SAToP modes
  • Wander compliant to MEF18 and G.8261
  • OC-3/STM-1 line, and DS1/E1 interfaces
  • Applications:
  • TDM over Packet
  • Wireless backhaul systems
  • Wireline network migration


The AC2560 TDM over Packet device implements Circuit Emulation Services Interworking Functions (CES IWF) for a fully channelized OC-3 or STM-1 capacity and 16 additional DS1/E1 TDM ports. Each of the DS1 or E1 channels are processed individually to provide a highdensity Gateway between TDM over SONET/SDH and TDM over packet.

The device integrates all functions for TDM transport gateway applications in wireless backhaul systems: SONET/SDH line interface with 1+1 APS protection, VT-1.5/VC-12 mappers, E1/DS1 framers, TDMoP IWF, and packet header processing.

The AC2560 implements the SAToP and CESoPSN modes defined by IETF, MEF, MFA and ITU. These support transport of transparent DS1/E1 channels, or provide bandwidth efficient nx64 fractional channels.

Each TDM channel can be configured independently for adaptive, differential or retiming clock recovery mode, and each channel may operate at a different clock rate.

The integrated DS1/E1 framers enable fault and performance monitoring, including test pattern insertion and loopback. The device supports Ethernet, VLAN, IP and MPLS PWE3 packet headers, and a dual Gigabit Ethernet interface.

The device is ideally prepared for new protocols or standards evolution due to its FPGA based design.

Evaluation systems are available for system level testing.


  • TDM over Packet CES IWF for 84+16 DS1s, 63+16 E1s
  • SAToP or CESoPSN transport mode selectable per channel (RFC4553 and RFC5086)
  • Configurable amount of TDM data per packet
  • Clock recovery mode selectable per channel: adaptive, differential or retiming mode
  • RTP header for differential clock (RFC3550)
  • Jitter and wander compliant to MEF18, ITU-T G.8261 and G.823 / G.824 for traffic interfaces
  • Configurable jitter buffer size
  • Extensive set of CES fault and performance monitoring points
  • The integrated SONET/SDH framer/mapper supports SOH/POH, pointer processors, and VT-1.5/VC-12 mappers
  • DS1/E1 framers provide alarm, fault and performance monitoring, and support for loopbacks and PRBS maintenance functionality
  • Integrated packet header processor for MAC addresses, VLAN tags, IP and MPLS PWE3 headers


  • 2 OC-3/STM-1 line interfaces
  • 16 TDM interfaces to LIU at 1.544 or 2.048 Mb/s
  • Dual GbE SerDes or interface to external PHY
  • Clock: 19.44 MHz
  • DDR2 DRAM for jitter buffer
  • 16-bit CPU interface

Applications and Block diagram

TDMoP aggregation application

Typical system applications for the AC2560 include:

  • High density TDM over packet equipment
  • Aggregation or gateway card Carrier-Class Ethernet Switch or IP/MPLS router
  • RNC or BSC controller network interface card
  • CMTS cable head-end
  • AMC I/O cards for ATCA and MicroTCA

Device block diagram and interfaces

A companion device, the AC2150 – 32x DS1/E1 TDMoP, targets TDM CES line cards and CPE applications. The AC2560 and AC2150 are based on the same processing core and allow for seamless end-to-end interworking.

For more information about the specifications, please contact us.