High Level Features
- TDM over Packet gateway for up to 336 DS1 or 252 E1 channels
- CESoPSN and SAToP mappings
- Jitter and wander compliant to G.8261 and G.823/G.824
- STM4/OC12 line interface
- Applications:
- TDM over packet aggregation nodes
- Wireless backhaul
- Wireline
network migration
Overview
The AC2380 TDM over Packet Gateway device implements Circuit Emulation Services Interworking Functions (CES IWF) for a fully channelized OC-12/STM-4. Each of the 336 DS1 or 252 E1 channels embedded on the line interface are processed individually to provide a high-density Gateway between TDM over SONET/SDH and TDM over Packet.Each of the embedded DS1 or E1 channels may be asynchronously clocked on ingress and the reassembly function supports independent clock recovery for the TDM data towards the line interface.
Each channel operates in either adaptive or differential clock recovery mode.
The AC2380 implements the IETF and MEF8 defined SAToP and CESoPSN modes. These allow transport of either the full DS1/E1 channels, or bandwidth efficient fractional channels. Integrated SONET/SDH framers/mappers and DS1/E1 framers enable fault and performance monitoring, including test pattern insertion and loopback. The device supports Ethernet, VLAN, MPLS and IP/UDP PWE3 packet headers and a SPI-3 bus towards the packet network.
The device is ideally prepared for new protocols or standards evolution due to its FPGA based design.
Features
CES IWF for up to 336 DS1 or 252 E1 channels
SAToP or CESoPSN transport mode selectable per channel
SAToP: unstructured agnostic payload transport
CESoPSN: transport of fractional E1/DS1
Configurable amount of TDM data per packet
Clock recovery mode selection per channel: adaptive or differential mode
RTP header for differential clock: RFC3550
RTP time stamp programmable at N * 8kHz
Jitter and wander compliant to ITU-T G.8261 and G.823 / G.824 for traffic interfaces
Programmable initial and maximum jitter buffer per port
Packet resequencing and missing packet detection with TDM frame replication
The integrated SONET/SDH framer/mapper supports SOH/POH, pointer processors, and VT1.5/VC12 mappers
DS1/E1 framers provide alarm, fault and performance monitoring and supports loopbacks and PRBS maintenance functionality
Integrated Ethernet MAC enables flexible packet header processing of MAC addresses, VLAN tags, MPLS and IP/UDP PWE3 headers.
Interfaces
OC-12 or STM-4 line interface
SPI-3 packet bus or dual GbE
Clock: 19.44 MHz
RAM interface
16-bit CPU interface
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