High Level Features
- TDM over Packet solution for DS1/E1
- CESoPSN and SAToP TDM mappings
- Jitter and wander compliant to G.8261 and G.823/G.824
- Integrated framers and dual GbE ports
- Applications:
- TDM over Packet CPE
- TDM over Packet aggregation nodes
- Wireless backhaul systems
- Wireline network migration
Overview
The AC2150 TDM over Packet device implements Circuit Emulation Services Interworking Functions (CES IWF) for 32 DS1/E1 TDM channels.Each of the TDM ports may be asynchronously clocked on ingress and the reassembly function supports independent clock recovery for the TDM data on egress. Each channel operates in either adaptive and differential clock recovery mode.
The AC2150 implements the IETF and MEF8 defined SAToP and CESoPSN modes. These allow transport of either the full DS1/E1 channels, or bandwidth efficient fractional channels. The integrated DS1/E1 framers enable fault and performance monitoring, including test pattern insertion and loopback. The device supports Ethernet, VLAN and MPLS PWE3 packet headers and a dual Ethernet interface.
The device is ideally prepared for new protocols or standards evolution due to its FPGA based design.
Features
- TDM over Packet CES IWF for 32 DS1/E1 ports
- SAToP or CESoPSN transport mode selectable per channel (RFC4553 and RFC5086)
- SAToP: unstructured agnostic payload transport
- CESoPSN: transport of fractional DS1/E1
- Configurable amount of TDM data per packet
- Clock recovery mode selection per channel: adaptive or differential mode
- RTP header for differential clock: RFC3550
- RTP time stamp programmable at N * 8 kHz
- Jitter and wander compliant to ITU-T G.8261 and G.823 / G.824 for traffic interfaces
- Programmable initial and maximum jitter buffer per port, up to 250 ms
- Packet resequencing and missing packet detection with TDM frame replication
- Integrated DS1/E1 framer provides alarm, fault and performance monitoring and supports loopbacks and PRBS maintenance functionality
- Integrated Ethernet MAC enables flexible packet header processing of MAC addresses, VLAN tags and MPLS PWE3 headers
Interfaces
- TDM interface to LIU at 1.544 or 2.048 Mb/s
- Dual RGMII/RTBI interfaces to PHY or SerDes
- Clock: 19.44 MHz
- DDR2 SDRAM buffer: 16 Mb x 16
- 16-bit CPU interface
Technology and Package
- 65 nm CMOS technology
- 1.2V / 2.5V / 3.3V power supply
- 484-pin 23 x 23 mm FBGA package
- Typical power dissipation < 1.5 Watt
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